Implementation of Low Transition Lfsr Test Pattern for Logic Bist
نویسندگان
چکیده
A Low Transition LFSR(LT-LFSR) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors which are given to Circuit under Test (CUT) to reduce the power consumption by CUT. This technique of generating low power test patterns is performed by increasing the co-relativity between the consecutive vectors by reducing the number of bit flips between successive test patterns. The proposed architecture increases the correlation among the vectors generated by LT-LFSR with negligible impact on test length. Verilog HDL is used as HDL language. The results were analysed using Xilinx for simulation and synthesis. The experimental result shows overall reduction in the total power consumption of the BIST circuitry.
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